Article ID: 000075651 Content Type: Troubleshooting Last Reviewed: 11/09/2011

cpri_rx_cnt_sync port Description and Frame Synchronization FSM in CPRI MegaCore Function User Guide are Incorrect

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The description of the cpri_rx_cnt_sync port (bits [4:2] of the extended_rx_status_data bus) in the CPRI MegaCore Function User Guide is incorrect for CPRI MegaCore function versions 10.0 and 10.1. The description in the Extended Rx Status Signals table in Chapter 5, Signals incorrectly describes the port, and the description of the initialization sequence for the testbenches, in Chapter 7, Testbenches, incorrectly implies this port has value 0x2 when frame synchronization completes.

    In addition, Figure 4-10 in Chapter 4, Functional Description is mislabeled. The state labeled XSYNC3 should instead be labeled HFNSYNC1, and the state labeled HFNSYNC should instead be labeled HFNSYNC2.

    The correct description of this port tells you that the port indicates the current state number (starting from zero rather than one) among the states whose category is indicated by the cpri_rx_state port (bits [1:0] of the extended_rx_status_data bus). For example, if the value of cpri_rx_state is 2’b10, the frame synchronization machine is in an XSYNC state. The cpri_rx_cnt_sync port tells you which XSYNC state the machine is in: if cpri_rx_cnt_sync has value 2’b00, the machine is in the state XSYNC1, and if it has value 2’b01, the machine is in state XSYNC2. Refer to the frame synchronization state machine figure in Chapter 4, Functional Description, with the modifications described in this erratum.

    Therefore, when cpri_rx_state has value 2’b11, cpri_rx_cnt_sync cannot have value 0x2. The frame synchronization machine has only two HFNSYNC states. After frame synchronization completes, the value of cpri_rx_cnt_sync is 3b’001, not 3b’010 as erroneously indicated in the Testbenches chapter.

    If you interpret the cpri_rx_cnt_sync port according to the description in the user guide, you wait for a value that will never appear to signal the HFNSYNC state of the CPRI frame synchronization machine.

    Resolution

    Interpret the cpri_rx_cnt_sync port (bits [4:2] of the extended_rx_status_data bus) according to this erratum rather than according to the description in the Signals chapter of the CPRI MegaCore Function User Guide.

    This issue is fixed in version 11.0 of the CPRI MegaCore Function User Guide.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices