Article ID: 000075630 Content Type: Troubleshooting Last Reviewed: 11/25/2024

Why does the eCPRI IP assert mac_source_sop and mac_source_valid after the mac_source_ready is de-asserted?

Environment

    Intel® Quartus® Prime Pro Edition
    CPRI
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to the ready latency of the eCPRI IP's mac_source_ready is 3 clock cycles, you may observe the mac_source_sop and mac_source_valid are asserted after the mac_source_ready is de-asserted.

Resolution

This is an expected behavior of the IP.

This information has been updated in the eCPRI IP User Guide.

Related Products

This article applies to 2 products

Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs

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