Article ID: 000075626 Content Type: Product Information & Documentation Last Reviewed: 01/27/2023

How do I enable or disable the Advanced Error Detection (AER) for my Intel® Stratix®10 PCIe* Hard IP core?

Environment

    Intel® Quartus® Prime Pro Edition
    Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
    Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
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Description

The AER function is enabled by default for all Intel® Stratix® 10 PCIe* Hard IP cores.  The user cannot disable this function.

 

 

 

 

Resolution

This information has been added to all the Intel® Stratix® 10 PCIe* Hard IP user guides.

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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