Article ID: 000075626 Content Type: Product Information & Documentation Last Reviewed: 02/26/2018

How do I enable or disable the Advanced Error Detection (AER) for my PCIe* Hard IP core?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The AER function is enabled by default for all Intel® Stratix® 10 PCIe* Hard IP cores.  The user cannot disable this function.

     

    Resolution

    No work around is required.

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