Article ID: 000075585 Content Type: Troubleshooting Last Reviewed: 04/29/2021

Why does the Intel® Agilex™ F-Series FPGA Development Kit fail to correctly link train in a PCIe* Gen3 system?

Environment

  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Quartus® II Subscription Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Intel® Agilex™ F-Series FPGA Development Kit has (SW7.1) default position is se to ON. SRIS Mode.
    This can cause PCIe* link instability problems especially in older Gen3 systems.

    Resolution

    To work around this potential problem, set SW7.1 to the OFF position (Common Refclk architecture), especially when using the card in older Gen3 systems.

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.