Article ID: 000075564 Content Type: Product Information & Documentation Last Reviewed: 08/29/2012

How to handle the input port cfglink2csrpld of the SV PCIe HIP?

Environment

    Quartus® II Subscription Edition
    PCI Express
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The port cfglink2csrpld is an undesired port in the HIP variation file. In the SV PCIe user guide there're no any descriptions regarding this signal.

 

Resolution

 You can connect the port cfglink2csrpld to "0" in your design. This port will be removed in Quartus II 12.0.

Related Products

This article applies to 1 products

Stratix® V GX FPGA

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