Critical Issue
Due to a problem with the Intel® Quartus® Prime Software version 21.2 and earlier, the gmii16b_rx_latency of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP output signal may potentially drift between 0 (min) and 0x3FFFFF (max) when Tx clock (tx_serial_clk), Rx clock (rx_cdr_refclk), link partner Tx data channel reference clock and recommended 80MHz latency_measure_clk of the IP core share a common clock source.
As a result, the generated Rx timestamps are not accurate, and the measured delay/offset is much larger than expected in IEEE 1588 applications. However, the gmii16b_tx_latency signal is not impacted by this problem. This problem only impacts 1G and 2.5G IEEE 1588 operations. 5G and 10G IEEE 1588 operations are not affected.
Modify IP core latency_measure_clk clock frequency from 80MHz to either 79.98MHz or 80.02MHz to avoid this problem.
This modification can also be applied to the 80MHz sampling clock frequency of TOD Synchronizer Intel® FPGA IP and will
not affect PTP timestamping accuracy.
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.