Article ID: 000075561 Content Type: Troubleshooting Last Reviewed: 07/14/2021

Why is the ready allowance smaller than the read latency of RX and TX Avalon® Streaming interfaces in the Intel® Arria® 10 Hard IP for PCI Express?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 21.2 and earlier, you may see the ready latency and the ready allowance of RX and TX Avalon® Streaming values of "3" and "0", which conflicts with the Avalon® Streaming specification that ready allowance should be equal or greater than ready latency.

    Resolution

    The ready allowance is in fact the same as the ready latency. You can ignore this display error.

    This problem is planned to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

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