Article ID: 000075561 Content Type: Troubleshooting Last Reviewed: 11/25/2024

Why is the ready allowance smaller than the read latency of RX and TX Avalon® Streaming interfaces in the Arria® 10 Hard IP for PCI Express?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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Description

Due to a problem in the Quartus® Prime Pro Edition Software version 21.2 and earlier, you may see the ready latency and the ready allowance of RX and TX Avalon® Streaming values of "3" and "0", which conflicts with the Avalon® Streaming specification that ready allowance should be equal or greater than ready latency.

Resolution

The ready allowance is in fact the same as the ready latency. You can ignore this display error.

Related Products

This article applies to 1 products

Intel® Arria® 10 FPGAs and SoC FPGAs

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