Article ID: 000075552 Content Type: Troubleshooting Last Reviewed: 02/13/2023

Why do I see small hold time violations in the "H-tile Hard IP for Ethernet Intel® FPGA IP"?

Environment

    Intel® Quartus® Prime Pro Edition
    Low Latency 100G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
    Ethernet
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Critical Issue

Description

Due to a problem in the Intel® Quartus® Pro Software version 18.0 and earlier, you might see small hold time violations in the "H-tile Hard IP for Ethernet Intel® FPGA IP."

 

 

Resolution

To work around this problem, try another fitter seed to avoid these timing violations.

This problem is fixed in Intel® Quartus® Prime Pro Edition Software version 18.1.

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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