Article ID: 000075552 Content Type: Troubleshooting Last Reviewed: 06/20/2018

Why do I see small hold time violations in the "H-tile Hard IP for Ethernet Intel® FPGA IP"?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Low Latency 100G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
  • Ethernet
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    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Pro software version 18.0 and earlier, you might see small hold time violations in the "H-tile Hard IP for Ethernet Intel® FPGA IP".

    Resolution

    To work around this problem, try another fitter seed in order to avoid these timing violations.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Pro software.

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