Article ID: 000075533 Content Type: Troubleshooting Last Reviewed: 08/14/2018

Why do I get "min_pulse_width" timing violations on my 1588/PTP 10/25G E-tile Hard IP for Ethernet Intel® FPGA IP core?

Environment

  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Ethernet
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    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime software version 18.0.1, you might see "min_pulse_width" timing violations in the 10/25G 1588/PTP E-tile Hard IP for Ethernet Intel® FPGA IP core. 

    Resolution

    There is no workaround for this issue.

    This issue is scheduled to be fixed in a future release of the Intel® Quartus® Prime software. 

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