Article ID: 000075516 Content Type: Troubleshooting Last Reviewed: 03/10/2021

Why does the Intel® L-/H-Tile Avalon® streaming IP for PCI Express* generate an MSI interrupt when either the msi_enable bit of the MSI Message Control Register or the Bus Master Enable bit of the PCI Command Register are not asserted?

Environment

  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 SX SoC FPGA
  • Intel® Stratix® 10 GX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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    Description

    The Intel® L-/H-Tile Avalon® streaming IP for PCI Express* does not check the status of the either the MSI Enable bit of the MSI Message Control Register or the Bus Master Enable bit of the PCI Command Register, and will generate a single dword Memory Write TLP to signal a MSI interrupt on the PCI Express* link every time that app_msi_req signal gets asserted.

    Resolution

    To work around this problem, the user application logic must validate the status of the MSI Enable and Bus Master Enable bits before asserting app_msi_req signal.

    This information is scheduled to be added in a future release of the Intel® L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) IP for PCI Express* User Guide.

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