Article ID: 000075512 Content Type: Error Messages Last Reviewed: 08/21/2023

Error (suppressible): ../../altera_rs_ser_dec_191/sim/rs2_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "in0_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® FPGA IP Reed-Solomon Encoder/Decoder II IP-RSCODECII
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the Reed Solomon II Intel® FPGA IP in the Intel® Quartus® Prime Pro Edition Software version 21.1 and earlier, you may observe the above error when simulating the VHDL simulation model in Modelsim* software.

    Resolution

    To work around this problem, you can use the Verilog simulation model.

    Related Products

    This article applies to 3 products

    Intel® Cyclone® 10 GX FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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