Description
Due to an issue in the PCIe® Hard IP PMA, the link may get stuck in the Detect.Active state.
This is due to the transceiver receiver detect logic not returning a PHYSTATUS pulse on the PIPE interface to the Hard IP core if the low period of two consecutive TxDetectRx is less than 544 ns.
This issue affects Stratix® IV GX, Stratix IV GT and Arria® II GX devices.
Resolution
Manually change the Hard IP reset logic to assert crst and srst signal for at least 1 us.
You can use the files below to view the changes required for both Avalon® Streaming (Avalon-ST) and Avalon Memory Mapped (Avalon-MM) interfaces to satisfy the requirement above.
- top_rs_hip (.v): Added reset logic can be found on lines 181-211. Put these lines in your <instantiation name>_rs_hip.v file for Avalon-ST interfaces.
- pcie_compiler_0 (.v) : Added reset logic can be found on lines 648-684. Put these lines in your instantiation file for Avalon-MM interfaces.
- pcie_compiler_0 (.vhd): Added reset logic can be found on lines 775-810. Put these lines in your instantiation file for Avalon-MM interfaces.
