Can I enable Multiple controllers clock sharing in ALTMEMPHY based High Performance Memory Controller in SoPC builder for Cyclone III and IV device?

Multiple controllers clock sharing option allows the controllers to share the static PHY clocks between multiple controllers that run on the same frequency and must share the same PLL reference clock.

However, there is limitation if you would like to enable this feature on Cyclone® III and Cyclone IV device family.

1. For design with two ALTMEMPHY instances, two PLLs will still be utilized.
   This is explained in another solution:
   Solution rd01192010_17
   
   
2. For ALTMEMPHY based memory controller, PLL should be fed on its fully compensated dedicated input pin to reduce Jitter and this is one of the timing model assumptions for PLL and clock network.
   
   "The reference input clock signal to the PLL must be driven by the dedicated clock input pin located adjacent to the PLL, or from the clock output signal from the adjacent PLL. To minimize output clock jitter, the reference input clock pin to the ALTMEMPHY PLL must not be routed through the core using global or regional clock networks."
   
   
3. Cyclone III and Cyclone IV devices do not have fully compensated dedicated clock input that could feed two PLLs.
4. 
   Such PLL clock network is only available on Arria® II GX, Stratix® III, Stratix IV device family.
   
   Arria II GX
   - CLK[8..11] for PLL_5 and PLL_6
   
   Stratix III, Stratix IV
   - CLK[0..3] for PLL_L2 and PLL_L3
   - CLK[4..7] for PLL_B1 and PLL_B2
   - CLK[8..11] for PLL_R2 and PLL_R3
   - CLK[12..15] for PLL_T1 and PLL_T2

For these reasons, multiple controllers clock sharing should not be used on Cyclone III and Cyclone IV device family.

Please consider to have seperate clock input for each memory controllers on Cyclone III and Cyclone IV device.