Article ID: 000075429 Content Type: Error Messages Last Reviewed: 05/20/2013

Error (261003): Can't continue the established JTAG communication. Reconnect communications cable and device

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software 12.1 SP1 and earlier, you may see this error when running the SignalTap™ II Logic Analyzer. This problem occurs due to incorrect optimization of the JTAG TDO path. This problem affects designs targeting Stratix® V, Arria® V, and Cyclone® V devices.

    Resolution

    To avoid this problem, properly constrain the JTAG TDO path and recompile your design. To properly constrain the JTAG TDO path, add the following constraints to your Synopsys Design Constraints (.sdc) file.

    if { [string equal quartus_fit $::TimeQuestInfo(nameofexecutable)] }
    { set_max_delay -to [get_ports { altera_reserved_tdo } ] 0 }

    This problem has been fixed and the path is properly constrained beginning with the Quartus II software version 13.0.

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    Related Products

    This article applies to 15 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Arria® V GX FPGA
    Cyclone® V GX FPGA
    Stratix® V GS FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Stratix® V E FPGA
    Cyclone® V SE SoC FPGA

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