Article ID: 000075423 Content Type: Troubleshooting Last Reviewed: 08/14/2018

Intel® Arria® 10 Gen3 PCIe* Endpoint is not compatible with PCIe* Gen4 capable system.

Environment

  • Intel® Arria® 10 GX FPGA
  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Intel® Arria® 10 Gen3 PCIe* IP core will treat Gen4 Data Link Features Exchange as unsupported DLLP type (as per the PCIe* 3.0 spec), unsupported DLLP type is not being flagged as valid DLLP, so does not ungate the InitFC.

    When this happens, no error is reported by the Intel® Arria® 10, this is expected.

    Resolution

    To work around this problem, Disable the Data Link Feature Exchange in PCIe Gen4 system [Base spec 4.0 chapter 7.7.4.2 Data Link Feature Capabilities Register (Offset 04h)] to be compatible with legacy hardware.

    This problem will not be fixed in a future release of the Intel® Quartus® Prime software.

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