Article ID: 000075400 Content Type: Troubleshooting Last Reviewed: 04/18/2023

Why is the inconsistent phase shift requirement of coreclock for Intel® Arria® 10 LVDS in the handbook and IP GUI summary?

Environment

  • ALTLVDS_TX
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to an error in LVDS Qsys GUI, it shows the core clock's phase is stuck at 0 degrees, while according to Intel® Arria® 10 handbook, it should be 180/SERDES factor. 

     

    Resolution

    This problem is fixed starting with Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook version 18.0.1

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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