Article ID: 000075379 Content Type: Troubleshooting Last Reviewed: 12/05/2017

Why does the Arria 10 Low Latency 10G MAC 1G/2.5G/10G (preset) Example Design show timing failure?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to an optimization problem, when using the 1G/2.5G/10G Arria® 10 Low Latency Ethernet MAC Example Design, setup timing failures may be seen between the soft PCS to 10G hard PCS transfer.

    Resolution

    To work around this setup timing failure, under-constrain the hold time of the transfer from soft PCS to 8G hard PCS to ease setup timing closure using the contraint below:

    if {![string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } {
    set_min_delay -from [get_keepers *|alt_mge16_phy_xcvr_term:*|tx_parallel_data_a10*] -to [get_keepers *|twentynm_pcs*:*|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg] -0.2ns
    }

    This problem is not scheduled to be fixed in a future version of the Intel® Quartus® Prime software.

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