Article ID: 000075372 Content Type: Troubleshooting Last Reviewed: 11/27/2017

Why is the waitrequest signal not asserted during reset when simulating my Stratix 10 40 Gbps Ethernet IP core?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Low Latency 40G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
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    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime software release 17.1, in simulation you will see the waitrequest signal stay deasserted (low) even while reset is asserted.  This is a violation of the Avalon®-MM specification and may result in errors from some testbenches, but is not a functional issue.

    Resolution

    To work around this problem, you can ignore this behavior, and either ignore the testbench errors or downgrade them to warnings.

    This problem is scheduled to be fixed in a future Quartus Prime software release.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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