Article ID: 000075166 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why isn't the synchronous clear signal in the I/O register used by the Quartus II software?


  • I O

    The I/O element (IOE) registers in the Stratix® and Cyclone® series of devices include a synchronous clear (sclr) signal, but there is no option in the Quartus® II software to use this sclr signal. For example, when you apply the Fast Output Register logic option to an output register, the Quartus II software places this register into the IOE, but the sclr signal of the IOE register is not used.  The Quartus II software uses a logic element (LE) to implement the synchronous clear functionality with an AND-gate on the clear signal and data signal.

    To take advantage of the synchronous clear signal, instantiate a DFFEAS primitive in your design and connect the sclr signal appropriately, as shown in the following example:

    module dff_with_sclr_packable_in_io (input d, clk, sclr, output q);
       dffeas my_packable_dff (.d(d), .clk(clk), .sclr(sclr), .q(q));

    By default this register is placed in the core of the device, but if you apply a Fast Input Register or Fast Output Register assignment, the register is packed into the I/O element and uses the sclr dedicated hardware.

    For more information about low-level primitives such as DFFEAS, refer to the Designing With Low-Level Primitives User Guide (PDF).

    Related Products

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    Stratix® FPGAs



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