Article ID: 000075138 Content Type: Troubleshooting Last Reviewed: 01/13/2012

Simulation Fails with NativeLink

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    When you use the NativeLink to run EDA RTL simulations for Verilog top-level file, the simulation fails and displays the following error message:

    #**Error: (vlog-7) Failed to open design unit file “test.vo” in read mode. # No such file or directory. (errno= ENOENT)

    Resolution

    On the Simulation page, under EDA Netlist Writer settings, set Format for output netlist to VHDL. Then, replace the following codes of the generated <variation>.v file to a single-line code before running the NativeLink simulation.

    Remove the following lines:

    //IPFS_FILES:test.vo //RELATED_FILES:stratix_components.vhd,altera_avalon_sc_fifo.v,auk_dspip_avalon_streaming_controller_hpfir.vhd,auk_dspip_avalon_streaming_source_hpfir.vhd,auk_dspip_math_pkg_hpfir.vhd,auk_dspip_lib_pkg_hpfir.vhd,test_ast.vhd,test.v

    Add the following line:

    //IPSF_FILES:NONE

    This issue will be fixed in future versions of the FIR Compiler II MegaCore function.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices