Description
The specification in the tables below shows the total external propagation delay (TEXT_DELAY) with respective to Active Serial (AS) clock frequency in Intel® Stratix® 10 and all Intel Agilex® devices.
When Internal Oscillator is used as configuration clock source:
| AS CLK Freq (MHz) | TEXT_DELAY min (ns) | TEXT_DELAY max (ns) |
|---|---|---|
| 25 | 0 | 24 |
| 58 | 0 | 20 |
| 77 | 0 | 20 |
| 115 | 0 | 20 |
When OSC_CLK_1 is used as configuration clock source:
| AS CLK Freq (MHz) | TEXT_DELAY min (ns) | TEXT_DELAY max (ns) |
|---|---|---|
| 25 | 0 | 24 |
| 50 | 0 | 24 |
| 71.5 | 0 | 35 |
| 100 | 0 | 24 |
| 108 | 0 | 22 |
| 125 | 0 | 18 |
| 133 | 0 | 15 |
Note: The data stated in the tables above is preliminary, pending silicon characterization.
Resolution
The Intel® Stratix® 10 Configuration User Guide and Intel Agilex® Configuration User Guide are updated starting with the Intel® Quartus® Prime Pro Edition Software version 20.3.
