Why does the IOPLL in Intel® Arria®10 FPGAs power up with an incorrect output clock when dynamic reconfiguration is enabled?

In some cases, due to race conditions at power-up, the IOPLL in Intel® Arria® 10 devices might start up with either an incorrect output clock frequency or an incorrect duty cycle or fail to achieve lock when dynamic reconfiguration is enabled.

To work around this, drive the input port 'mgmt_clk' of the IOPLL Reconfig Intel® FPGA IP core from the output port 'outclk' of another IOPLL Reconfig Intel FPGA IP and synchronize the mgmt_reset with this clock. This ensures the clock to the IOPLL Reconfig Intel FPGA IP core does not toggle at power up and allows the IOPLL to power up with correct parameters.