Article ID: 000074949 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I receive the following message: "Internal Error: Sub-system: VPR20K, File: 20k_arch/20k_route_timing.c, Line: 2434?"

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description You may get this internal error in the Quartus® II software version 1.0 if you have two occurrences of the THIRD_PARTY_EDA_TOOLS variable in your project settings file (.psf).

For example:

THIRD_PARTY_EDA_TOOLS(pci_top)
{
   EDA_TIMING_ANALYSIS_TOOL = "&ltNONE>";
   EDA_SIMULATION_TOOL = "MODELSIM (VERILOG HDL 
OUTPUT FROM QUARTUS)";
   EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = SYNPLIFY;
}
THIRD_PARTY_EDA_TOOLS(sdram_sdr_ecc_pci_ioreg)
{
   EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = SYNPLIFY;
}
To avoid this error, ensure that the .psf file specifies the THIRD_PARTY_EDA_TOOLS variable only once. This problem was fixed in the Quartus II software version 1.1.

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