The Deinterlacer II and Broadcast Deinterlacer IP cores do not support Qsys generation and synthesis. This issue affects any system using the Deinterlacer II or Broadcast Deinterlacer IP core that is generated in Qsys version 14.0 Arria 10.
To work around this issue, follow these steps:
Generate the IP cores in isolation using an earlier version of Qsys.
Then add the generated HDL file (located in the synthesis directory) to the 14.0 Arria 10 Quartus II project.
Remove the associated .qip file from the project.