No, the FPGA to HPS bridge must not be reset from the software. The following corrections are being made to the documentation.
Issue 530449: Intel Stratix 10 Hard Processor System Technical Reference Manual, version 2018.03.02. Chapter 12 Reset Manager, Section 12.3 Reset Signals.
f2s_bridge_rst_n must have a footnote. This footnote must state: "Software must never reset this bridge. This bridge must only be reset by POR/COLD/WARM reset."
Issue 543408: Intel Stratix 10 Hard Processor System Programming Reference Manual, version 2017.11.06. Page 7536, Section 2.31.10 i_rst_mgr_rstmgr.brgmodrst.fpga2soc description.
Change bit 2 “fpga2soc” description to the following: "Software must never write 0x1 to this bit. Software may only write 0x0 to this bit."
No Workaround/Fix.
Under normal use cases, the software must write 0x0 to this bit to bring this bridge out of reset. If a customer wants to reset this bridge, the customer must use POR or COLD, or WARM reset sequence.