Article ID: 000074764 Content Type: Product Information & Documentation Last Reviewed: 02/13/2023

How do I resolve the problem with an Intel® Stratix® 10 FPGA IOPLL not being able to obtain lock when the input refclk is driven by an output clock from the Intel Stratix 10 FPGA E-Tile?

Environment

    Intel® Quartus® Prime Pro Edition
    IOPLL Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The Intel® Stratix® 10 FPGA IOPLL is not being able to obtain lock when the input refclk is driven by an output clock from the Intel Stratix 10 FPGA E-Tile.

Resolution

You must perform user recalibration of the IOPLL after the output clocks from the Intel Stratix 10 FPGA E-Tile are stable.

Holding the Intel Stratix 10 FPGA IOPLL in reset until output clocks from the Intel Stratix 10 FPGA E-Tile are stable or pulsing the reset after the output clocks are stable will not resolve the Intel Stratix IOPLL unlocked state.

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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