Article ID: 000074689 Content Type: Product Information & Documentation Last Reviewed: 09/08/2017

How can I perform a Remote System Update on a Cyclone III or Cyclone IV device over a JTAG to Avalon MM Master Bridge?

Environment

  • JTAG to Avalon Master Bridge Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Remote System Update IP Core for Cyclone® III or Cyclone IV devices provides an Avalon MM (AVMM) interface to read and write to the core control and status registers to perform a successful configuration update. This can be done with a compatible AVMM Master component available in Quartus® Prime software without the need for an on-chip processor. 

    The JTAG-Avalon MM Master Bridge forms a direct interface between the user and the remote system update IP core, which allows users to perform reconfiguration via System Console over JTAG interface.

    The Remote Update IP Core Avalon-MM Registers that need to be configured over JTAG, while updating the configuration from a factory image to an application image are :

    1. Write to RU_WATCHDOG_TIMEOUT
      • Address offset is 0x20
      • Write a 12-bit timer value
    2. Read back from this register can be done to see if the watchdog timer value is written correctly . 
      • Address offset is 0x2C
      • Reads back the 12-bit timeout value
    3. Write to RU_WATCHDOG_ENABLE
      • Address offset is 0x30
      • Write 0x1 to Enable or 0x0 to Disable the Watchdog Timer
    4. Write to RU_BOOT_ADDRESS
      • Address offset is 0x40
      • Write a 32 bit start address which points to the start of the application image stored on the flash device. The FPGA shall boot from this address once reconfiguration is triggered. For example : 0x00400000
    5. Read back from this register can be done to see if the boot address for application image is written correctly.
      • Address offset is 0x4C
      • Reads back the 32 bit boot address.
    6. Write to RU_RECONFIG
      • Address offset is 0x74
      • Write 0x1 to trigger a reconfiguration

    Once a reconfiguration is triggered, the System Console loses its connection to the FPGA over JTAG. Users would need to launch a new session of System Console once the FPGA boots from the application image to re-establish a valid JTAG chain.

     

     

    Related Products

    This article applies to 2 products

    Cyclone® IV FPGAs
    Cyclone® III FPGAs