Article ID: 000074590 Content Type: Troubleshooting Last Reviewed: 08/30/2023

Why do I see a DQS write preamble (tWPRE) violation in hardware when using DDR3 or DDR2 SDRAM hard memory controller with UniPHY?

Environment

    Quartus® II Subscription Edition
    External Memory Interfaces Debug Component Intel® FPGA IP
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Description

Due to a problem in the Quartus® II software, when using the hard memory controller with UniPHY, a tWPRE timing violation might be observed when probing the signals with an oscilloscope. This issue occurs because the parallel termination circuitry (read OCT) does not switch to series termination mode early enough to prevent squelching of the DQS write preamble.

 

Resolution

This problem does not affect hardware operation. Please get in touch with Intel® IPS Support for more details.

 

Related Products

This article applies to 9 products

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