Article ID: 000074590 Content Type: Troubleshooting Last Reviewed: 12/30/2014

Why do I see a DQS write preamble (tWPRE) violation in hardware when using DDR3 or DDR2 SDRAM hard memory controller with UniPHY?

Environment

  • Quartus® II Subscription Edition
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    Description

    Due to a problem in the Quartus® II software ,when using the hard memory controller with UniPHY, there might be a tWPRE timing violation being observed when probing the signals with an oscilloscope. This issue occurs because the parallel termination circuitry (read OCT) does not switch to series termination mode early enough to prevent squelching of the DQS write preamble.

    Resolution

    This problem does not affect hardware operation. Please contact Altera mySupport for more details.

    Related Solution

    http://www.altera.com/support/kdb/solutions/fb142174.html

    Related Products

    This article applies to 9 products

    Arria® V GX FPGA
    Arria® V GT FPGA
    Arria® V GZ FPGA
    Cyclone® V GX FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA

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