Description
You can test a Serial Vector Format (SVF) file generated for Intel® FPGAs or CPLDs using the JTAG Chain Debugger tool in the Quartus® Prime software, by following the steps below :
1. In the Quartus Prime software, go to the Tools menu and select JTAG Chain Debugger
2. Go to the Edit Menu, select Hardware Setup to define your programming cable.
3. Click on the JTAG Chain Debugging tab.
4. Click on Open JTAG Chain Log...
5. Select your SVF file and click OK.
This will execute the SVF file to configure or program your Intel FPGA or CPLD with the SVF file.