Article ID: 000074556 Content Type: Troubleshooting Last Reviewed: 01/21/2014

Why does the Hard IP for PCI Express downtrain from Gen3 x8 to Gen3 x1 in simulation?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus II software version 12.1 and earlier, the Stratix V Hard IP for PCI Express testbench downtrains from Gen3 x8 to Gen3 x1.

    This problem only affects simulation and does not cause any problems in hardware.

    Resolution

    To work around this problem upgrade to software v12.1SP1 or later.

    Related Products

    This article applies to 5 products

    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Stratix® V GX FPGA
    Arria® V GZ FPGA
    Stratix® V FPGAs

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