Article ID: 000074553 Content Type: Troubleshooting Last Reviewed: 07/13/2023

Why are tREFI values in simulation and board measurement different from what is set in Altmemphy and UniPHY-based DDR2 SDRAM memory controller?

Environment

    Quartus® II Subscription Edition
    LPDDR2 SDRAM Controller with UniPHY Intel® FPGA IP
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Description

tREFI result in simulation and on the board might be larger than expected if you set tREFI to less than 7.8us in DDR/DDR2/LPDDR2 MegaWizard.

DDR/DDR2/LPDDR2 SDRAM IP has a MEM_TREFI parameter, which defines the tREFI parameter in terms of memory clock cycles.

 

Since the minimum value of this parameter is limited to 780, tREFI becomes larger when the memory clock is slower.

For example, tREFI for DDR2 SDRAM should be 3.9us at >85C. But if the DDR2 memory clock is 125MHz(8ns), the minimum tREFI value can be 8ns x 780 = 6.24us.

tREFI for DDR should be 7.8us. But if the DDR memory clock is 76.9MHz (13ns), the minimum tREFI value can be 13ns x 780 = 10.14us.

 

 

Resolution

As a workaround, if the DDR memory clock is below 100MHz or if you set tREFI to <7.8us on DDR2 memory, you can change the MEM_TREFI parameter in

*ddrx_controller_wrapper (Altmemphy-based IP) file or *_c0 (UniPHY-based IP) file to correct the tREFI value.

This problem has been fixed in Quartus® II Software Version 12.0.

Related Products

This article applies to 14 products

Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Arria® II GX FPGA
Arria® II GZ FPGA
Arria® V GT FPGA
Arria® V GX FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® III FPGAs
Cyclone® III LS FPGA
Cyclone® IV E FPGA
Cyclone® IV GX FPGA
Stratix® III FPGAs

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