Article ID: 000074506 Content Type: Troubleshooting Last Reviewed: 12/25/2019

Why is an user output pin in an unexpected state during initialization stage in Intel® Arria® 10 device?


  • Intel® Quartus® Prime Pro Edition

    You may see user output pins go into an unexpected state during initialization stage in Intel® Arria® 10 device. 
    This is because user logic and user I/O pins are activated gradually, not at the same time during initialization stage.


    An example is shown below. ( Figure of example )

    • An user input pin connects to the low active set port of a register.
    • This user input pin is kept low from power-up to user mode.
    • A data output port from the register connects to an user output pin.

    The user output pin is expected to keep high, because the user I/O pins are in input tri-state with weak pull-up during configuration stage and initialization state and the register is expected to be set to high by the set port in user mode.

    But use logic and user I/O pins are activated gradually during initialization stage.  When the register and the user output pin are activated faster than the input port and the initial state of the register is low, the output pin propagates low from the register until the input port is activated and the set port of the register becomes low.

    When an external device monitors an output from the Intel Arria 10 device, an unexpected state during initialization stage may affect the behavior of the external device.


    To work around this problem, use one of the following ways.

    • Workaround 1: Make the external device to ignore the state of the user output pin until INIT_DONE pin goes high (Figure of workaround 1)
    • Workaround 2: Keep the input state to the external devices proper using external logic until INIT_DONE pin goes high (Figure of workaround 2)
    • Workaround 3: Keep the output state of the Arria 10 device using user logic until internal INIT_DONE signal goes high (Figure of workaround 3)

    You can use internal INIT_DONE signal with the following WYSIWYG instantiation.


    << Verilog >>

    twentynm_controller u1 ( .initdonecore(<internal INIT_DONE wire name>) );


    << VHDL >>

    component twentynm_controller is

      port( initdonecore: out STD_LOGIC );

    end component;


    u1 : twentynm_controller

    port map( initdonecore => <internal INIT_DONE wire name> );


    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs



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