Article ID: 000074491 Content Type: Troubleshooting Last Reviewed: 10/14/2016

Why does execution of the KEY_VERIFY JTAG instruction return 0x0 (hex) after the tamper protection bit has been programmed in Stratix V, Arria V or Cyclone V devices?



The JTAG instruction, KEY_VERIFY is one of many non-mandatory JTAG instructions that are disabled when the tamper protection bit is enabled in Stratix® V, Arria® V or Cyclone® V FPGAs. When executing a non-mandatory instruction like KEY_VERIFY when the tamper protection bit is programmed, TDI points to the BYPASS register. Due to this, executing the KEY_VERIFY instruction when the tamper protection bit has been set will result in 0x0 (hex) being returned.


To check if the tamper protection bit has been programmed in a device, shift a user defined pattern in when executing the KEY_VERIFY instruction and check that the TDO pattern received has a \'0\' shifted in,

Example, assume you shift in 0x15A (1 0101 1010 in binary). If the tamper protection bit has been programmed, since KEY_VERIFY=BYPASS, you should expect 0 1011 0100 where the last 0 is the content of the BYPASS register.

Related Products

This article applies to 14 products

Arria® V GT FPGA
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Cyclone® V SE SoC FPGA
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Cyclone® V ST SoC FPGA