SerialLite III Streaming IP Core Missing a Verilog Design File When Using TCL Script to Run Simulation

When the Quartus II MegaWizard Plug-In Manager generates the SerialLite III Streaming IP core, four simulation directories are created in <variation_name>_src_sim (for aldec, mentor, synopsys, and cadence simulation tools). These directories contain the simulation files for you to run the simulation software.However, the control_word_decoder.v file is missing from the simulation directory and therefore, the simulation software reports an error when you try to run simulation using the TCL script.This missing file issue does not affect the simulation scripts in the example_testbench directory.

This issue affects the SerialLite III Streaming IP core in Quartus II software 13.0 release.

If you are using the TCL script or shell script in the <variation_name>_src_sim directory, you are required to manually add the control_word_decoder.v file into the script that you want to use. For example, if using Aldec simulation software, add the line below into the file list before you compile the rivierapro_setup.tcl script.vlog "./../../<variation_name>_src_example/seriallite_iii/example_testbench/control_word_decoder.v" -work <variation_name>_src

This issue is fixed in version 13.1 of the SerialLite III Streaming IP core.