Article ID: 000074377 Content Type: Troubleshooting Last Reviewed: 11/25/2024

What are valid data and twiddle factor widths for the FFT IP core?

Environment

  • Intel® Quartus® Prime Pro Edition
  • FFT Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The FFT IP core allows various combinations of data path width and twiddle factor width.  Within the code generating scripts for the FFT core there are several combinations that the data path width and twiddle factor widths are compared against before generation will proceed. There is one combination that was not accounted for in the script. If the data path width is less than 19 and the twiddle factor width is greater than 18, hardware will not be generated.

    Resolution

    Change your data path width or your twiddle factor width so they do not fall within the problem range, i.e., data path width less than 19 AND twiddle factor width greater than 18. For future FFT requirements we recommend using DSP Builder.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices