The IOPLL IP Core User Guide does not include information about the behavior of the locked output port.
The locked output port behaves in the following manner during the three stages of the PLL's locking into the input clock:
Stage 1: When the PLL is kept in active reset (reset = HIGH), the lock signal is LOW.
Stage 2: When the PLL is no longer in active reset (reset = LOW) but its input clock is not stable, the lock signal will be LOW as long as the PLL has not locked to the reference clock.
Stage 3: When the PLL is no longer in active reset (reset = LOW) and its input clock is stable, the lock signal exposed by the IP core goes through a digital filter. The filter only asserts the external lock signal when the incoming lock signal has been asserted for 25 clock cycles consecutively.
If the PLL does not lose lock after this, the external lock signal should not toggle when the PLL is trying to acquire lock. The external lock signal will be deasserted when the incoming lock signal is LOW (loss of lock) for 2 clock cycles consecutively.
The documentation will be updated in a future release.