Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 19.1 and later, this error will be issued in register transfer level (RTL) simulation using ModelSim when the design includes the ALTLVDS_RX IP core.
When using another simulator than ModelSim, an error for 'lvds_rx_reg_setting' will be issued as well.
To avoid this error, use one of the following workarounds:
• Use the suppress option along with vsim command when using the ModleSim ( ex. vsim -suppress 10000 )
Or
• Remove the lines for ALTLVDS_RX_component.lvds_rx_reg_setting from the top RTL of the ALTLVDS_RX IP
1) Open the top RTL of the ALTLVDS_RX IP using a text editor.
2) Remove the following lines:
<Verilog>
ALTLVDS_RX_component.lvds_rx_reg_setting = "ON"
<VHDL>
lvds_rx_reg_setting : STRING;
and
lvds_rx_reg_setting => "ON",
This problem has been fixed in the Intel® Quartus® Prime Standard Edition Software version 22.1.