Why does the Generic Serial Flash Interface Intel® FPGA IP fail to deassert nCS in write enable operation?

Due to a problem in Intel® Quartus® Prime software version 20.1 Pro Edition and Standard Edition and earlier, the Generic Serial Flash Interface Intel FPGA IP may fail to deassert nCS in write enable operation, when both the following conditions are met.

• Multiple memory operations are instructed in close succession from CSR port
• A read memory register operation such as read status, flag status register is instructed right after a write enable operation is instructed

When the problem occurs, nCS doesn’t deassert and DCLK unnecessarily toggles for a while even after the write enable command code is sent out.

To work around this problem, add the following number or more of interval cycles between instructions from CSR port.

The number of interval cycles between instructions = Baud rate divisor * 15  (IP input clock cycles)

This problem has been fixed since Intel Quartus Prime software version 20.3.