Article ID: 000074004 Content Type: Troubleshooting Last Reviewed: 07/04/2016

Why is flashsm_reset reported as an unconstrained clock in the PFL IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • MicroBlaster™ Fast Passive Parallel Software Driver
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    Description

    Due to a problem in the Quartus® Prime software version 16.0 and earlier, you may see flashsm_reset reported as an unconstrained clock. This occurs when you instantiate the Parallel Flash Loader (PFL) IP in a MAX® 10 device.

    Resolution

    Flashsm_reset is not a clock so it is safe to ignore this warning.

    This problem is scheduled to be fixed in a future release of the Quartus Prime software.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

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