Article ID: 000073999 Content Type: Troubleshooting Last Reviewed: 12/23/2022

Does the Cyclone® 10 Native Phy Transceiver IP offer tx_pma_elecidle input port?

Environment

    Intel® Quartus® Prime Pro Edition
    Transceiver Native PHY Intel® Arria® 10 Cyclone® 10 FPGA IP
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Description

Due to feature limitations, Native Phy Transceiver IP for Intel® Cyclone® 10 devices does not offer the option “Enable tx_pma_elecidle”. Hence tx_pma_elecidle input port is not offered in the IP.

Resolution

There is no workaround to force the transmitter into an electrical idle condition. Please use the transmitter reset pin, tx_analogreset, or tx_digitalreset to place the transmitter in reset instead of the tri-state condition.

Related Products

This article applies to 2 products

Intel® Programmable Devices
Intel® Cyclone® 10 GX FPGA

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