Article ID: 000073972 Content Type: Troubleshooting Last Reviewed: 08/02/2023

Info: mypll.xcvr_atx_pll_s10_htile_0: The current value "GX clock output buffer" for parameter "Primary PLL clock output buffer" (primary_pll_buffer) is invalid.

Environment

    Intel® Quartus® Prime Pro Edition
    L-Tile H-Tile Transceiver ATX PLL Intel® Stratix® 10 FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see the following message in the Stratix® 10 L-Tile or H-Tile ATX PLL IP Paramater Editor message pane when configuring your PLL for dynamic reconfiguration between GX and GXT modes using the configuration profiles feature.

Info: mypll.xcvr_atx_pll_s10_htile_0: The current value "GX clock output buffer" for the parameter "Primary PLL clock output buffer" (primary_pll_buffer) is invalid. Possible valid values are: "GXT clock output buffer."  

Resolution

The message indicates that the GX clock output buffer mode is invalid, but the message is green in color, indicating that it is valid.

The message refers to the output buffer mode for the inactive configuration and can be safely ignored.

Related Products

This article applies to 2 products

Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Programmable Devices

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