Article ID: 000073939 Content Type: Troubleshooting Last Reviewed: 05/17/2024

Why do I see Linux prints multiple “unexpected MSI” messages in the PCIe Root Port with MSI design?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • PCIe DMA Controller Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In a PCIe Root Port with an MSI design, the PCIe hard IP is connected to an MSI-GIC IP via a pipeline bridge.

    When Linux prints multiple “unexpected MSI” messages, you will observe unintended writes happen which do not belong to the MSI-GIC slave. 

    Resolution

    A workaround is to add a second slave to the PCIe master next to the vector slave (MSI-GIC IP). This slave could be a small on-chip memory, a custom register, or something else.

    With a second slave and "Automate Default Salve Insertion" Interconnect feature enabled, MSI-GIC will not receive those unintended writes.

     

     

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices