This problem may be seen when users have chosen the incorrect setting for edge capturing, thus preventing interrupt from being triggered.
In the PIO(Parallel I/O) Intel® FPGA IP core, if the option “Enable individual bit setting/clearing” is turned off, writing any value to the edge capture register will clear all bits in the register. This is a default setting in Nios® II count binary template.
For example:
/* Reset the edge capture register. */
IOWR_ALTERA_AVALON_PIO_EDGE_CAP(BUTTON_PIO_BASE, 0x0);
When the “Enable individual bit setting/clearing” option is turned on, writing a 1 to a particular bit in the register clears only that bit. For example:
/* Reset the edge capture register bit 0 and bit 1. */
IOWR_ALTERA_AVALON_PIO_EDGE_CAP(BUTTON_PIO_BASE, 0x3);
To work around this problem, choose the correct settings for the option “Enable individual bit setting/clearing.”
- If enable bit-clearing for the edge capture register is turned off, writing any value to the edge capture register clears all bits in the register.
- If enable bit-clearing for the edge capture register is turned on, writing a 1 to a particular bit in the register clears only that specific bit.
The PIO Intel® FPGA IP core user interface has been enhanced on description at the option “Enable individual bit setting/clearing,” starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 21.1