Article ID: 000073890 Content Type: Product Information & Documentation Last Reviewed: 08/09/2023

How to avoid ACP Dependency Lockup in Intel® Cyclone® V SoC, Arria®V SoC, and Arria®10 SoC


  • Intel® Quartus® Prime Pro Edition

    Under certain conditions, you may have an ACP dependency lockup in Arria® and Cyclone® SoCs. Below are some example scenarios of how that might happen:

    1.  ARM CPU accesses FPGA fabric using a device memory access. This type of access causes the CPU pipeline to stall until the access is completed.
    2.  The FPGA fabric state machine issues coherent access to HPS over ACP to be able to respond to the HPS access.
    3.  The ACP receives access, but it requires SCU to do a cache maintenance operation to complete it. However, the cache maintenance operation cannot be completed as the CPU pipeline is stalled—the system is deadlocked.



    Avoid needing to coherently access back the HPS through ACP from the fabric to complete access coming from HPS, as this may cause a deadlock situation.

    You can achieve the same result by breaking the functionality into smaller pieces. For example, initiate an operation with access, then use a second access to determine the status of the operation.

    Related Products

    This article applies to 3 products

    Arria® V SX SoC FPGA
    Cyclone® V SX SoC FPGA
    Intel® Arria® 10 SX SoC FPGA