How to avoid ACP Dependency Lockup in Intel® Cyclone® V SoC, Arria®V SoC, Arria®10 SoC

You may have an ACP dependency lockup in Arria® and Cyclone® SoCs under certain conditions. Below are some example scenarios on how that might happen:

1.  ARM CPU accesses FPGA fabric, using a device memory access. This type of access causes the CPU pipeline to stall until the access is completed.
2.  The FPGA fabric state machine issues coherent access to HPS, over ACP, in order to be able to respond to the HPS access.
3.  The ACP receives access, but it requires SCU to do a cache maintenance operation in order to complete it. However, the cache maintenance operation cannot complete as the CPU pipeline is stalled. The system deadlocks.

Avoid needing to coherently access back the HPS through ACP from the fabric in order to complete access coming from HPS, as this may cause a deadlock situation.

You can achieve the same result by breaking the functionality into smaller pieces. For example, initiate an operation with access, then use a second access to determine the status of the operation.