Article ID: 000073823 Content Type: Troubleshooting Last Reviewed: 06/30/2015

Timing setup violations in SerialLite III Streaming IP Core Design Example

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

The SerialLite III Streaming IP Core design example will run into timing setup violations in ACDS Quartus II version 15.0 due to the removal of false path in the seriallite_iii_streaming_demo.sdc file.

Resolution

Manually update the seriallite_iii_streaming_demo.sdc with the following constraint:

set_false_path -to [get_cells -compatibility *demo_mgmt*dp_sync_stage_1|o[*]]

Related Products

This article applies to 1 products

Intel® Programmable Devices

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