Article ID: 000073759 Content Type: Troubleshooting Last Reviewed: 04/14/2014

Why does the Quartus II software incorrectly show “Critical Warning: Timing analysis was performed on core hps_sdram_p0 using Quartus II v13.1 with a preliminary timing model and constraints..”?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® II software version 13.1 Update 3 and later, you may see the the following critical warnings when compiling a Cyclone® V SoC HPS design.

Critical Warning: Timing analysis was performed on core hps_sdram_p0 using Quartus II v13.1 with a preliminary timing model and constraints. You must regenerate this IP in a future version of Quartus II to update the timing constraints to match the timing mode

The timing models are final for the Cyclone V SoC devices as listed in the ACDS version 13.1 Update Release Notes:

Altera Complete Design Suite Version 13.1 Update Release Notes

Resolution

It is safe to ignore this critical warning.

This problem is scheduled to be fixed in a future release of the Quartus II software.

Related Products

This article applies to 3 products

Cyclone® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.