When a blank serial configuration device is attached to Cyclone II device, and the field programmable gate array (FPGA) device is configured directly via the JTAG interface, intermittent failure may occur. This is due to FPGA actively driving out on the DCLK signal while the FPGA is in the Active Serial (AS) mode reconfiguration loop.
When the failure occurs the FPGA device does not enter user mode and function accordingly. When the serial configuration device is programmed, the FPGA will function as expected with the image loaded from the configuration device in AS mode. DCLK signal stops toggling once the FPGA is configured and breaks the reconfiguration loop. A new image can then be configured into the FPGA via JTAG mode. The FPGA device functions as expected.
This setup uses two 10-pin download cable headers on the board. This allows configuring the FPGA directly via the JTAG interface and programing the serial configuration device in-system via the AS interface. The MSEL pins are set to AS mode.
For Quartus II users: To ensure that the FPGA can be configured successfully directly via JTAG interface, users would need to set the 'Halt on-chip configuration controller' option 'ON' under Tools --> Options --> Programmer before starting the configuration with Quartus II programmer. This includes using the Serial Flash Loader IP because JTAG is used for configuring the Cyclone II device. They do not need to recompile their Quartus II designs after setting this Option to ON.
Or: For customers who are not using Quartus II programmer to configure the FPGA, they would need to insert the CONFIG_IO instruction before starting the JTAG configuration cycle. The OPCODE of CONFIG_IO instruction for Altera devices can be downloaded from BSDL Files.
Figure 1. Combining AS and JTAG configurationView Full Size