Article ID: 000073685 Content Type: Product Information & Documentation Last Reviewed: 02/19/2014

How do I use the en4b_addr input signal on the ALTASMI_PARALLEL megafunction?

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    Description

    The introduction of serial configuration devices with greater than 128Mb capacity such as the EPCQ256 device requires the use of  a 4-byte addressing mode instead of the default 3-byte addressing mode.

    The ALTASMI_PARALLEL megafunction has an additional input signal, en4b_addr for this purpose when generated for a configuration device with greater than 128Mb capacity.

    To change from 3-byte addressing mode to 4-byte addressing mode,you need to pull the write enable signal (wren) high and en4b_addr signal for at least one clock cycle.  After the megafunction receives the en4b_addr command, it asserts the busy signal to indicate operation is in progress.

    Figure 1 shows an example performing the change to 4-byte addressing mode.

     

    Figure 1

    Related Products

    This article applies to 2 products

    Arria® V GX FPGA
    Intel® FPGA Configuration Devices