What Is User Interrupt (UINTR)? Is It Supported on Intel® Xeon® 6 Processors?

The User Interrupt (UINTR) on Intel® Xeon® Processors, including the Intel® Xeon® 6 Processors, is a feature related to the processor's interrupt handling mechanism. 

Overview of User Interrupt (UINTR)

User Interrupt is a mechanism by which the system can notify the processor of events that require immediate attention. On Intel® Xeon® Processors, user interrupts are typically handled through the Advanced Programmable Interrupt Controller (APIC) or the local APIC (LAPIC) in the case of multiple processors.

User Interrupt (UINTR) support is determined by the processor's capabilities and system software configuration. The following details are relevant:

Enumeration and Enabling: Processor support for user interrupts is enumerated using the CPUID instruction with parameters (EAX=7, ECX=0):EDX[5].  If this bit is set, the processor supports UINTR.

Software enables user interrupts by setting bit 25 (UINTR) in control register CR4. This enables user-interrupt delivery, notification identification, and user-interrupt instructions.

XSAVE Management: The UINTR feature is XSAVE-managed, meaning aspects of the feature are enumerated as part of the XSAVE feature set. The XSAVE feature set can operate on UINTR state only if enabled (CR4.OSXSAVE = 1) and configured to manage UINTR state (IA32_XSS[14] = 1).

User-Interrupt State: The UINTR state comprises specific MSRs (Model-Specific Registers) such as IA32_UINTR_HANDLER, IA32_UINTR_STACKADJUST, IA32_UINTR_MISC, IA32_UINTR_PD, IA32_UINTR_RR, and IA32_UINTR_TT. These are managed as supervisor state components.

UINTR on Intel® Xeon® 6 Processors

For Intel® Xeon® 6 Processors, UINTRs can be related to various system events such as:

• Hardware Interrupts: Originating from peripherals or other system components requiring service.
• Software Interrupts: Generated by software for tasks like handling system calls or signaling between processes.

The Intel® Xeon® 6 Processors follow the general interrupt handling mechanisms outlined in Intel's documentation, including the use of the LAPIC for interrupt delivery in multi-processor systems.

Compatibility

As described on Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture, User Interrupt (UINTR) is supported on Intel® Xeon® 6 Processors with E-core (Sierra Forest).

Intel® Xeon® 6 Processors with P-core Processors (Granite Rapids) are not documented as supporting this feature.

To confirm support for UINTR on Intel® Xeon® Processors, you would need to check the CPUID instruction output for the specific processor model.

Review the guides listed below, as they provide detailed instructions.