The following information lists the new features introduced with the Intel® VROC 8.0 release for Windows*. To learn about the latest updates of Intel® VROC for Windows*, refer to the Intel® Virtual RAID on CPU (Intel® VROC) Release Notes for Windows*.
The Intel® VROC OOB management interface supports only NVMe* drives and Intel® VROC (VMD NVMe* RAID) volumes. SATA drives and Intel® VROC (SATA RAID) volumes can be managed through other Intel® VROC (in-band) interfaces. In the Intel® VROC OOB management solution, the BMC is the entry point for the requests from a management network. It processes the requests, for example management commands, and sends them to the MCTP endpoint exposed by the Intel® OOB-MSM, via MCTP over PCIe. The Intel® OOB-MSM works as MCTP bridge, it receives requests from BMC and sends them to Intel® VROC OOB host software over the Intel® VMD mailbox register. The Intel® VROC OOB host software component periodically polls the Intel® VMD mailbox register for new requests. The Intel® VROC OOB host software performs the requested action and sends the response to the BMC in the opposite way. A high-level view of the solution is presented in the figure below.
There are two PCIe ports designed and controlled under the Platform Controller Hub (PCH), Emmitsburg, and this feature with LED management is implemented in the circuit and the on-board secondary CPLD. Designers need to implement the same or similar logic control as this CPLD does to control two LEDs designed on-board to represent the RAID status.
When two or more different LED patterns are applicable to the same drive, the Intel® VROC driver for Windows* shall apply the following order in terms of precedence:
With the Intel® VROC 8.0 release, the GUI application has a new and fresh design.
When this warning message condition is detected from one major version or two minor versions difference, the Intel® VROC GUI will not allow to manage the storage controller but can provide a set of functionalities corresponding to the lowest driver version. The Intel® VROC GUI utility still can start even if there is no driver installed.
Fishhawk Falls (FHF) Platform | This new feature is not applicable to Fishhawk Falls (FHF) platforms with the Intel® VROC release version 8.0.0.3483. |
Intel® VROC is a software RAID solution for NVMe* and SATA drives. Intel® VROC starting with version 8.0.1 introduces the Intel® VROC Pre-EFI Initialization Module (PEIM) to support the BIOS recovery scenario during boot.
The Intel® VROC PEI module for SATA provides access to RAID volumes and SATA drives connected to the Intel® SATA controller. The Intel® VROC PEI module for Intel® Volume Management Device (Intel® VMD) provides access to RAID volumes and NVMe* drives connected to a single Intel® VMD controller.
Both modules have common code base with PEI interface implementation and RAID logic. The main difference between them is the different transport implementations (AHCI vs. Intel® VMD and NVMe*). Every Intel® VROC PEI module installs two PEIM-to-PEIM interfaces (PPI), defined in the PI specification:
These PPIs are used to read data from pass-through drives and RAID volumes, enumerated by the Intel® VROC PEI modules.
Intel® VROC 8.0 PEI modules have several limitations:
When the Intel® VROC product displays how the Intel® Volume Management Device (Intel® VMD) controller enumerates the drives, the drive information is showing in the Intel® VROC HII like in the figure below. The information is not straightforward and not easy to interpret. To present the drive location information in a user-friendly manner, Intel® VROC offers a protocol that will allow customers to report how the drives are connected and how customers would like the information reported in the customer platform.
The Intel® VROC family of products introduces support for a third SATA controller on the Intel® Platform Controller Hub (PCH). Starting with the Intel® C741 chipset, Intel® VROC will provide support for the third SATA controller (tSATA) when the controller is set for RAID mode. Refer to the respective platform design documentation for how the tSATA ports are laid out.
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